Imec’s process technology roadmap to 2036

The imec roadmap will take us from 7 nm to 0.2 nm or 2 ångström by 2036, keeping an introductory pace of two to two-and-a-half years.

First, the continuous advances in lithography will be key to further dimensional scaling: traditional lithography uses light, and, today, the wavelength of light is greater than the required accuracy of the patterns.

That's why Extreme UV (EUV) lithography has been introduced. It is now appearing on more and more functional production belts for volume manufacturing. EUV will take us from the five nanometer-generation to two nanometers.

To go smaller we need an updated version of EUV, high-NA EUV, with bigger lenses. These will have a diameter of one meter with an accuracy of 20 picometers.

For high-NA EUV, the first prototype, which is being developed by ASML, will be available in 2023.

Insertion in high-volume manufacturing is expected sometime during 2025 or 2026. In order to derisk the introduction in manufacturing, imec, together with ASML, has set up a very intensive program to develop all the key enabling building blocks, such as the mask technology and materials using wet or dry UV resist, metrology, and optics characterization.

Today almost all chip manufacturers build microchips with FinFET transistors. However, when entering the 3nm-generation, FinFETs suffer from quantum interference, causing disruptions in the operation of microchips.

Next in line is the Gate-All-Around (GAA) or nanosheet transistor, built up as a stack of nanosheets, it will offer improved performance and improved short channel effects. This architecture will be essential from 2 nm onwards.

Samsung, Intel, and TSMC have already announced that they will introduce GAA transistors in their 3nm and/or 2nm nodes.

The forksheet transistor is an imec invention, even denser than the nanosheet transistor, extending the gate-all-around concept to the 1 nm generation.

The forksheet architecture introduces a barrier between the negative and positive channels, enabling the channels to come closer together.

This architecture is expected to enable a cell-size shrink of 20 percent.

Further scaling can be realized by putting the negative and positive channels on top of each other, referred to as the Complementary FET (CFET) transistor, a complex vertical successor to the GAA.

It significantly improves density but comes at the expense of increased process complexity, especially to contact the source and drains of the transistors.

In time, CFET transistors will incorporate new ultra-thin 2D monolayer materials with an atomic thickness, like Tungsten disulfide (WS2) or molybdenum.

This device roadmap, combined with the lithography roadmap, will bring us to the ångström age.

Two other challenges are playing at the system level of these sub 2nm-transistors.

The memory bandwidth cannot keep up with CPU performance.

The processor can't run faster than the pace at which data and instructions become available from the memory.

To knock down this ‘memory wall’, memory must come closer to the chip.

An interesting approach for tearing down the memory wall is 3D system-on-chip (3D SOC) integration, which goes beyond today's popular chiplet approaches.

Following this heterogeneous integration approach, the system is partitioned into separate chips that are concurrently designed and interconnected in the third dimension.

It will allow for example to stack a SRAM memory layer for level-1-Cash right on the core logic devices, enabling fast memory to logic interaction.

To achieve extreme high bandwidth off-module connectivity, optical interconnects, integrated on photonics interposers are being developed.

Regarding system-related challenges, getting enough power into the chip and getting the heat out becomes more difficult.

However, a solution is in sight: the power distribution now runs from the top of the wafer through more than ten metal layers to the transistor. Imec is currently working on a solution from the backside of the wafer.

We will sink power rails into the wafer and connect them to the backside using nano-through-silicon vias in wider, less resistive materials.

This approach will decouple the power delivery network from the signal network, improving the overall power delivery performance, reducing routing congestion, and, ultimately, allowing further standard cell height scaling